The simultaneous processing of a large number of semiconductor die in a parent wafer is well known. After all common processing steps have been carried out, the die are singulated, or separated from one another for packaging or other application.
It has been found that while every location on a wafer is expected to react to processing identically to other locations, in fact some areas react differently than others. Thus, in copending application Ser. No. 10/728,482, filed Dec. 4, 2003 in the names of Kohji Andoh and Davide Chiola (IR-2076) the contents of which are incorporated herein by reference, the resistivity at the surface of a wafer may vary, and is adjusted so that the final wafer presents a uniform resistivity over its entire surface.
It has been found, particularly for the production of trench type MOSFETs, or other trench devices, that the trenches at the outer peripheral areas of the wafer are deeper than those in the central areas of the wafer. This results in a reduced breakdown voltage (BVDSS) of die which are (or were) located in the outer peripheral areas of the wafer.
It would be desirable to adjust the process so that the die taken from the outer peripheral areas of the wafer have characteristics such as BVDSS which more closely match those of die taken from the more central body areas of the wafer.